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W81E381D/W81E381AD
FULL SPEED USB INTEGRATED MICROCONTROLLER
W81E381D/W81E381AD
Full Speed USB Integrated Microcontroller
W81E381D/W81E381AD
W81E381D/AD Data Sheet Revision History
Pages 1 2 n.a. P.9, P.11, P.14, P.35, P.36, P.47, P.48 P.14, P.53, P.54 Dates 03/2001 09/2001 Version 0.50 0.51 Version on Web n.a. n.a. Main Contents First published 1. Modify pin function of SCIO & SCCLK 2. Revise register description of SCCR (AC) and SCECR (AD) 3. Revise the USB register descriptions 1. Revise register description of CHPCON (CF) 2. Modify the description of SFRCN & CHPCON
3
01/2002
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n.a.
4 5 6 7 8 9 10
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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TABLE OF CONTENTS
1. General Descriptions: .........................................................................................................................................5 2. FEATURES: .......................................................................................................................................................6 3. PIn configuration ...............................................................................................................................................7 3.1 W81E381D 48-pin LQFP PINOUT............................................................................................................7 3.2 W81E381AD 100-pin LQFP PINOUT .....................................................................................................10 4. Programming interface.....................................................................................................................................13 4.1 Register map ..............................................................................................................................................13 4.2 FLASH Category - Descriptions Summary ............................................................................................14 4.3 SC Category - Descriptions Summary .....................................................................................................14 4.4 USB Category - Descriptions Summary...................................................................................................15 4.5 Individual register description .................................................................................................................16 4.5.1 Register Descriptions - USB Power Control Registers (E7)..........................................................16 4.5.2 Register Descriptions - USB Interrupt System SFRs (A2) ............................................................18 4.5.3 Register Descriptions - USB Interrupt System SFRs (C0) ............................................................19 4.5.4 Register Descriptions - USB Interrupt System SFRs (B1) ............................................................20 4.5.4 Register Descriptions - USB Interrupt System SFRs (B1) ............................................................20 4.5.5 Register Descriptions - USB Function SFRs (E1) .........................................................................21 4.5.6 Register Descriptions - USB Function SFRs (F1) .........................................................................23 4.5.7 Register Descriptions - USB Function SFRs (8F) .........................................................................24 4.5.8 Register Descriptions - USB Function SFRs (E6) .........................................................................26 4.5.9 Register Descriptions - USB Function SFRs (E4) .........................................................................27 4.5.10 Register Descriptions - USB Function SFRs (E3) .........................................................................28 4.5.11 Register Descriptions - USB Function SFRs (E5) .........................................................................30 4.5.12 Register Descriptions - USB Function SFRs (E2) .........................................................................32 4.5.13 Register Descriptions - USB Function SFRs (F6) .........................................................................34 4.5.14 Register Descriptions - USB Function SFRs (F4) .........................................................................35 4.5.15 Register Descriptions - USB Function SFRs (F3) .........................................................................36 4.5.16 Register Descriptions - USB Function SFRs (F5) .........................................................................38 4.5.17 Register Descriptions - USB Function SFRs (F2) .........................................................................40 4.5.18 Register Descriptions - USB Device SFRs (B7)............................................................................42 4.5.19 Register Descriptions - USB Device SFRs (BF)............................................................................43 4.5.20 Register Descriptions - SC Interrupt SFRs (AA)...........................................................................44 4.5.21 Register Descriptions - SC Interrupt SFRs (AB) ...........................................................................45 4.5.22 Register Descriptions - SC Control SFRs (A3)..............................................................................46 4.5.24 Register Descriptions - SC Control SFRs (AC).............................................................................47 4.5.25 Register Descriptions - SC Control SFRs (AD).............................................................................48 4.5.26 Register Descriptions - SC Control SFRs (AE, A4) ......................................................................49 4.5.27 Register Descriptions - SC Control SFRs (A5)..............................................................................50 4.5.28 Register Descriptions - SC Data SFRs (A6, A7) ...........................................................................51 4.5.29 Register Descriptions - ISP Registers (C4, C5).............................................................................52 4.5.30 Register Descriptions - ISP Registers (C6, C7).............................................................................53 Publication Release Date: January 2002 Revision 0.52
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4.5.31 4.5.32 Register Descriptions - uC Control Registers (CF) .......................................................................54 Register Descriptions - uC Control Registers (D4, D5) ................................................................55
4.6 MTP-ROM PROGRAMMING ................................................................................................................56 5. Security..............................................................................................................................................................57 6. Electrical Characteristics .................................................................................................................................58 7. Mechanical information ...................................................................................................................................59 7.1 W81E381D 48 LQFP (7x7x1.4mm footprint 2.0mm) PACKAGE ........................................................59 7.2 W81E381AD 100 LQFP (14x14x1.4 mm footprint 2.0mm) PACKAGE...............................................60 8. TYPICAL APPLICATION ...............................................................................................................................61 8.1 W81E381D reference schematic ...............................................................................................................61 8.2 W81E381AD reference schematic ............................................................................................................62
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1. GENERAL DESCRIPTIONS:
The W81E381 is 8052-based USB device with 20 Kbytes flash memory. By integrating the USB1.1 transceiver, SIE, enhanced 8032 code, 20K Flash memory, extra 256 Byte RAM, power regulator, and general purpose I/O in single chip, W81E381D/W81E381AD creates a very low cost-effective solution that provides superior time-to-market advantages. The GPIO provides an easy interface to popular interface, such as ATAPI, EPP, RS232, MCU and DSP interface.
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2. FEATURES:
* * * * * * * * * * * * * * Fully compliant with the Universal Serial Bus Specification version 1.1. Support USB Suspend and Resume operation for power-down standby. Support USB remote wake up function. Embedded microprocessor--8052 with extra 256Bytes RAM for data processing/storage, 20 Kbytes of In-System Programmable Flash memory. Internal generated 12MHz clock for 8052 use (the same as standard 8052 uses 24 MHz clock outside) External and separated 8052 clock input supported 6 clock per instruction 8052 core Flash support 512Byte erase block Software setting, 2KByte block programmable write protection for Flash memory 6-Mhz crystal/oscillator input for both Full speed application with limited EMI affection Support smart card interface, including serial interface memory card, and SCIO & SCCLK pins could be programmed as GPIO pins by registers setting Built-in 3.3V power regulator for single 5V power operation Internal PLL for USB and SC requirements Support one Control endpoint for command (8 bytes), and four endpoints 1, 2, 3, 4 (Bulk In, Bulk Out Interrupt In, and Interrupt Out) for data. BulkIn, BulkOut with 16 bytes FIFO InterruptIn, InterruptOut with 8 bytes FIFO W81E381D: 48LQFP package W81E381AD: 100LQFP package
* *
Ordering Information Part Number W81E381D W81E381AD Package Type 48-PIN LQFP 100-PIN LQFP Production Flow Commercial, 0oC to +70oC Commercial, 0oC to +70oC
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3. PIN CONFIGURATION
3.1 W81E381D 48-pin LQFP PINOUT
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3.1.1 48- pin LQFP package description
SYMBOL USB Pins AVDD AVSS V33 D+ DXTALI XTALO Extra Pins PLLEN uC Pins RVED1-3 RST P0.0-P0.7 X IL I/O D 21,41, 48 29 46,47, 8,9, 15,16, 17,18 10 11 12 13 14 22 25 26 28 Reserved pins. Leave these pins floating. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. PORT 0: Function is the same as that of the standard 8052. I 27 PLL enable pin; Schmitt-trigger pull up input PWR PWR PWR I/O I/O I O 1 2 5 3 4 36 37 Analog 5V power supply Analog 5V power ground USB DC power 3.3V output. USB signal (+) USB signal (-) Crystal input. Use 6M Hz crystal. A 6 MHz clock source may also be used. Crystal output. TYPE PIN NO DESCRIPTIONS
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.2
I/O I/O I/O I/O I/O I/O I/O I/O I/O H
It is a high drive I/O pad. Used as a GPIO pin for memory-type SC It is a high drive I/O pad. Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC GPIO & remote wakeup pin GPIO & external interrupt pin It's a bi-directional I/O port with internal pull-ups. It can be programmed to be an output-latched port like an on-chip 74373, or a buffer input port like an on-chip 74244.
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3.1.1 48-PIN LQFP package DESCRIPTION, continued
SYMBOL P3.0-P3.1 P3.4-P3.7 UC-XI UC-XO Pow er Pins VSS VDD SDA SCL SCPWR SCIO SCCLK SCRST SCPRSNT
TYPE PIN NO I/O H I/O H I O PWR PWR I/O I O I/O O I 34,35 42,43, 44,45 24 23 19,38 20,39 6 7 33 30 32 40
DESCRIPTIONS PORT 3: Function is the same as that of the standard 8052. PORT 3: Function is the same as that of the standard 8052. uC Crystal input. uC Crystal output. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. Data input/output of serial interface Clock input of serial interface Smart card power supplier enable pin Smart card serial data input/output pin or GPIO pin Smart card clock output (default 3M Hz) or GPIO pin Smart card reset signal Smart card existed indicator. Schmitt-trigger input
Serial Interface
Smart Card Reader Pins
O (I/O) 31
*Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain, PWR: Power pins, X: Floating
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3.2 W81E381AD 100-pin LQFP PINOUT
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3.2.1 100-pin LQFP package description
SYMBOL USB Pins AVDD AVSS V33 D+ DXTALI XTALO SCPWR SCIO SCCLK SCRST SCPRSNT Extra Pins PLLEN XCVREN TESTENB Pow er Pins VSS VDD SDA SCL PWR PWR I/O I 37,81 38,82 8 9 GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. Data input/output of serial interface Clock input of serial interface I I I 53 95 11 12 PLL enable pin; Schmitt-trigger pull up input XCVR enable pin; Schmitt-trigger pull up input Software connection enable pin; Schmitt-trigger pull up input Test enable pin; Schmitt-trigger pull up input PWR PWR PWR I/O I/O I O O I/O O I 1 2, 3 6 4 5 79 80 66 63 65 83 Analog 5V power supply Analog 5V power ground USB DC power 3.3V output. USB signal (+) USB signal (-) Crystal input. Use 6MHz crystal. A 6MHz clock source may also be used. Crystal output. Smart card power supplier enable pin Smart card serial data input/output pin or GPIO pin Smart card clock output (default 3MHz) or GPIO pin Smart card reset signal Smart card existed indicator. Schmitt-trigger input TYPE PIN NO DESCRIPTIONS
Smart Card Reader Pins
O (I/O) 64
SOFTCNEN I
Serial Interface
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3.2.1 100-pin LQFP package description, continued
SYMBOL TYPE uC Pins EA I
PIN NO 96
DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be present on the bus if the EA pin is high and the program counter is within the 64 KB area. Otherwise they will be present on the bus. EXTERNAL uC51 ENABLE: to enable external processor PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin.
UC51EN I PSEN OH
97 39
ALE
OH
86
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. An ALE pulse is omitted during external data memory accesses. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. uC Crystal output. uC Crystal input.
RST UC-XO UC-XI P0.0 - 7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
IL O I I/O D I/O I/O I/O I/O I/O I/O I/O I/O
61 45 46
93,94,14,15 PORT 0: Function is the same as that of the standard 8052. 29,31,32,33 16 18 19 26 27 43 51 52 It is a high drive I/O pad. Used as a GPIO pin for memory-type SC It is a high drive I/O pad. Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC Used as a GPIO pin for memory-type SC GPIO & remote wakeup pin GPIO & external interrupt pin
P2.0 - 7 I/O H
41,42,55,56 PORT 2: Bi-directional I/O port with internal pull-ups. Also provides the 57,59,60,84 upper address bits for external memory. Can be programmed as outputlatched port as on-chip 74373, or a buffer input port as an on-chip 74244. 68,69,35,36 PORT 3: Function is the same as that of the standard 8052. 88,89,90,91
P3.0 - 7
I/O H
*Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain, PWR: Power pins
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4. PROGRAMMING INTERFACE
4.1 Register map
0/8 F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 FIFLG xxx0 x000 IP xxx0 0000 P3 1111 1111 IE 0xx0 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 IEN1 0xxx 0x0x -xxx ---- SCIER 0000 0000 FIE xxx0 x000 SBUF xxxx xxxx SCISR 0000 0000 SCSR 0000 0000 SCCR 0001 0110 SCBDR 0000 0001 SCECR 0000 0000 SCCBR 0000 0001 SCGTR 0000 0000 SCRDR 0000 0000 SFRAL 0000 0000 SFRAH 0000 0000 SFRFD 0000 0000 PSW 0000 00x0 AUX 0000 0110 PMPR1 xxxx xx00 PMPR2 0000 0000 CHPENR 0000 0000 CHPCON 0xx0 0000 SFRCN 0000 0000 SCON DCON ACC 0000 0000 EPCON 001x 0101 000x 0000 RXSTAT 0000 0000 RXDAT 0000 0000 RXCON 0xx0 0xxx RXFLG x0xx 1000 RXCNT xxxx 0000 FPCON 0000 0000 000- 1000 B 0000 0000 EPINDEX xxxx xxx0 TXSTAT 0xx0 0000 TXDAT xxxx xxxx xxx0 0000 TXCON 0xxx 0xxx TXFLG x0xx 1000 TXCNT xxxx 0000 USBIDR 1/9 2/A 3/B 4/C 5/D 6/E 7/F FF F7 EF E7 DF D7 CF C7 BF B7 AF SCTDR 0000 0000 A7 9F 97 TMOD 0000 0000 SP 0000 0011 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 FADDR 0000 0000 PCON 00xx 0000 7/F 8F 87
8052 uC SFRs USB SFRs Flash SFRs Smart Card SFRs Endpoint-Indexed SFRs by EPINDEX
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4.2 FLASH Category - Descriptions Summary
Mnemonic SFRCN SFRFD SFRAH SFRAL Mnemonic CHPCON PMPR2 PMPR1 ISP Registers The Control Register of uC ISP Function The Programming Data Register for Flash Memory The High Byte of the Programming Address The Low Byte of the Programming Address uC Control Registers On-chip Register Programming Control Blocks Blocks Address S:C7H S:C6H S:C5H S:C4H Address S:CFH S:D5H S:D4H
- LBP7 - - LBP6 - - LBP5 - - FD7 HA7 LA6 - FD6 HA6 LA6 OEN FD5 HA5 LA5
Description
CEN FD4 HA4 LA4 CTRL3 FD3 HA3 LA3 CTRL2 FD2 HA2 LA2 CTRL1 FD1 HA1 LA1 CTRL0 FD0 HA0 LA0
Description
- LBP4 - - LBP3 - - LBP2 - - LBP1 HBP1 FPROGEN LBP0 HBP0
Flash Memory Protective Configure Register Flash Memory Protective Configure Register
4.3 SC Category - Descriptions Summary
Mnemonic SCIER SCISR Mnemonic SCSR SCCR SCECR SCGTR SCBDR SCCBR Mnemonic SCRDR SCTDR SC Interrupt SFRs SC Interrupt Enable Register SC Interrupt Status Register SC Control SFRs SC Status Register SC Control Register SC Extended Control Register SC Guard Time Control Register SC Baud Rate Divider Register SC Clock Base Register SC Data SFRs SC RX Data Register SC TX Data Register Address S:AAH S:ABH Address S:A3H S:ACH S:ADH S:AEH S:A4H S:A5H Address S:A6H S:A7H
RD7 TD7 RD6 TD6 RD5 TD5 - - CRDRST BIT7 BIT7 BIT7 - - PWRENP BIT6 BIT6 BIT6 - - VCC_EN BIT5 BIT5 BIT5 - CLKSTPL - BIT4 BIT4 BIT4 - - ESCPTI SCPTI WCE WCI - TDI
Description
RDRE RDRI PBE PBRI EXIE EXI - EXI_16
Description
SCPRSNT S_CK1 - BIT3 BIT3 BIT3 - S_CK0 CLKSTP BIT2 BIT2 BIT2 - EPE SCIO BIT1 BIT1 BIT1 CA EXINTH SCRRST BIT0 BIT0 BIT0
Description
RD4 TD4 RD3 TD3 RD2 TD2 RD1 TD1 RD0 TD0
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4.4 USB Category - Descriptions Summary
Mnemonic FPCON Mnemonic FIE FIFLG IEN1 Mnemonic EPCON* EPINDEX FADDR RXCNT* RXCON* RXDAT* RXFLG* RXSTAT* TXCNT* TXCON* TXDAT* TXFLG* TXSTAT* Mnemonic DCON SCON USB Power Control SFRs Function Power Control Register USB Interrupt System SFRs USB Function Register USB Function Register Interrupt Interrupt Enable Flag Address S:E7H Address S:A2H S:C0H S:B1H Address S:E1H S:F1H S:8FH S:E6H S:E4H S:E3H S:E5H S:E2H S:F6H S:F4H S:F3H S:F5H S:F2H Address S:B7H S:BFH
TEST_MODE SIERXDE SCGPIOSL SIELSE SCIOGPE SECKPAT RXSTL - - - RXCLR RD7 - RXSEQ - TXCLR TD7 - TXSEQ TXSTL - A6 - - RD6 RXFIFO RXSETUP - - TD6 TXFIFO - CTLEP - A5 - - RD5 - STOVW - - TD5 - - - - EA - - - FRXIE4 FRXD4 - FPD FRWUPE FWKP
Description
URDIS URST FRWU FRSM FSUS
Description
FTXIE3 FTXD3 - FRXIE2 FRXD2 EFSR FTXIE1 FTXD1 - FRXIE0 FRXD0 EF FTXIE0 FTXD0 -
USB Interrupt Enable Register USB Function SFRs Endpoint Control Register Endpoint Index Register Function Address Register Receive FIFO Byte-Count Register Receive FIFO Control Register Receive FIFO Data Register Receive FIFO Flag Register Endpoint Receive Status Register Transmit FIFO Byte-Count Register Transmit FIFO Control Register Transmit FIFO Data Register Transmit FIFO Flag Register Endpoint Transmit Status Register USB Device SFRs Device Control Register 1 SIE Control Register
Description
- - A4 BC4 RXFFRC RD4 - EDOVW BC4 - TD4 - TXFLUSH RXIE - A3 BC3 RXISO RD3 RXEMP RXSOVW BC3 - TD3 TXEMP TXSOVW RXEPEN EPINX2 A2 BC2 - RD2 RXFULL RXVOID BC2 - TD2 TXFULL TXVOID TXOE EPINX1 A1 BC1 - RD1 RXURF RXERR BC1 - TD1 TXURF TXERR TXEPEN EPINX0 A0 BC0 - RD0 RXOVF RXACK BC0 - TD0 TXOVF TXACK
Description
SCIOGPD STODPAT SCCLKGPE SEOSMOD1 SCCLKGPD SEOSMOD0 PTRWUEN SEOPMOD1 CONPUEN SEOPMOD0
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4.5 Individual register description
4.5.1 FPCON Register Descriptions - USB Power Control Registers (E7) Address: S:E7H System Reset State: 0000 0000H USB Reset State: 000-1000H
Function Power Control Register. Facilitates the control and status relating to power-down mode, remote-wakeup enable, function wakeup, USB reset separation, remote wake-up control and function resume/suspend. 7 FPD Bit Number 7 6 FRWUPE Bit Mnemonic FPD 5 FWKP 4 FRIE 3 FRST 2 FRWU 1 FRSM 0 FSUS
Function Function Power-down Mode Bit: When set, activates USB power-down mode. This bit should only be set if the FSUS bit is also set. Cleared by hardware when an interrupt or reset occurs. Recommends to set with PCON.0 & PCON.1 together. Function Remote Wake-up Enable Bit: Set if the function is currently enabled to request remote wake-up. This bit is modified through the Set/ClearFeature (DEVICE_REMOTE_WAKEUP). When `0', the function can't initiate remote resume via either FW setting FRWU or triggered by external signal. Note that don't set this bit until after the Function is enumerated and the host issued a SetFeature(DEVICE_REMOTE_WAKEUP). Function Wake-up Bit: 1=wake-up. Set by hardware when wake-up events occur, asserts signal FWKP to high. This bit is "Or"ed with FSUS and FRSM to generate the interrupt. Cleared by firmware when servicing the function. Firmware should prioritize FRSM over FWKP if both bits are set simultaneously. Note: This bit is not set if FRWUPE=0 or FRSM=1 or FRWU=1. USB Reset Disable: When cleared by firmware, a chip reset occurs upon receiving of a USB reset signal. This resets all USB blocks, microcontroller, and all peripherals. When set by firmware, a USB reset signal just only reset all USB blocks, but not reset microcontroller and all peripherals. Microcontroller can be interrupted via the interrupt source URST that is set by the completion of a received USB reset. Note that IEN1. EA/EFSR/EF doesn't be reset furring USB reset signaling if this bit is set.
6
FRWUPE
5
FWKP
4
URDIS
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continued
Bit Number 3
Bit Mnemonic URST
Function USB Reset Flag: This flag will be set by hardware when a USB reset occurs and completes, regardless of when the EFSR bit in the IEN1 register is enabled or disabled. The URST also serves as the interrupt bit, "Or"ed with FRSM and FSUS bits to generate an interrupt. Should be cleared by firmware when serving the USB reset interrupt. Function Remote Wake-up Bit: This bit is used by the function to issue an wake-up signal (K) to host when uC is interrupt by the FWKP=1. Set by firmware to make driving resume signal. It will be cleared by hardware when remote-wakeup is completed. FW can poll and wait FRWU=0 to know the completion of remote-wakeup. Note: Don't set this bit unless the function is suspended (FSUS=1 and FRSM=0). Function Resume Bit: 1= resume. Set by hardware when "start" or "end" of up stream port resume is occurred. This bit is "Or"ed with FSUS to generate the interrupt. Cleared by firmware when servicing the function suspend/resume interrupt. Note: This bit is not set if remote wakeup is active (FRWU=1). Firmware should prioritize FRSM over FSUS if both bits are set simultaneously. Function Suspend Bit: 1= suspend. Set by hardware when the device is set to suspend. This bit is "Or"ed with FRSM to generate the interrupt. During the function suspend ISR, firmware should set the FPD bit to enter the suspend mode. Cleared by hardware when a function resume occurs.
2
FRWU
1
FRSM
0
FSUS
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4.5.2 FIE Register Descriptions - USB Interrupt System SFRs (A2) Address: S:A2H Reset State: XX00 0000H
Function Interrupt Enable Register: Enables and disables the received and transmit done interrupts for the function endpoints. 7 Bit Number 7 6 5 4 3 2 1 0 6 Bit Mnemonic FRXIE4 FTXIE3 FRXIE2 FTXIE1 FRXIE0 FTXIE0 5 FRXIE4 4 FTXIE3 3 FRXIE2 2 FTXIE1 1 FRXIE0 0 FTXIE0
Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Function Receive Interrupt Enable 4: Enables the receive done interrupt for function endpoint 4 (FRXD4). Function Transmit Interrupt Enable 3: Enables the transmit done interrupt for function endpoint 3 (FTXD3). Function Receive Interrupt Enable 2: Enables the receive done interrupt for function endpoint 2 (FRXD2). Function Transmit Interrupt Enable 1: Enables the receive done interrupt for function endpoint 1 (FTXD1). Function Receive Interrupt Enable 0: Enables the receive done interrupt for function endpoint 0 (FRXD0). Function Transmit Interrupt Enable 0: Enables the transmit done interrupt for function endpoint 0 (FTXD0).
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4.5.3 FIFLG Register Descriptions - USB Interrupt System SFRs (C0) Address: S:C0H Reset State: XX00 0000H
Function Interrupt Flag Register: Contains the USB function's transmit and receive done interrupt flags for non-isochronous endpoints. 7 Bit Number 7 6 5 4 3 2 1 0 6 Bit Mnemonic FRXD4 FTXD3 FRXD2 FTXD1 FRXD0 FTXD0 5 FRXD4 4 FTXD3 3 FRXD2 2 FTXD1 1 FRXD0 0 FTXD0
Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Function Receive Done Flag 4: (read, write clear) For endpoint 4. This bit is cleared when firmware writes `1' to it. Function Transmit Done Flag 3: (read, write clear) For endpoint 3. This bit is cleared when firmware writes `1' to it. Function Receive Done Flag 2: (read, write clear) For endpoint 2. This bit is cleared when firmware writes `1' to it. Function Transmit Done Flag 1: (read, write clear) For endpoint 1. This bit is cleared when firmware writes `1' to it. Function Receive Done Flag 0: (read, write clear) For endpoint 0. This bit is cleared when firmware writes `1' to it. Function Transmit Done Flag 0: (read, write clear) For endpoint 0. This bit is cleared when firmware writes `1' to it.
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4.5.4 IEN1 Register Descriptions - USB Interrupt System SFRs (B1) Address: S:B1H System Reset State: 0XXX 0X0XH USB Reset with PCON1.URDIS=1: -XXX -X--XH
USB Interrupt Enable Register: Contains the enable bits for the USB interrupts. 7 EA Bit Number 7 6 Bit Mnemonic EA 5 4 3 EFSR 2 Function Global Interrupt Enable: Setting this bit enables the interrupts that are individually enabled by bit3 & bit1 of this register. Clearing this bit disables all interrupts. Note: This bit doesn't be reset when a USB reset occurs if FPCON.URDIS=1. Reserved: Reserved: Reserved: Enable Function Suspend/Resume: Function suspend/resume interrupt enable bit. Note This bit doesn't be reset when a USB reset occurs if FPCON.URDIS=1. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Enable Function: Transmit/receive done interrupt enable bit for non-isochronous USB function endpoints. Note: This bit doesn't be reset when a USB reset occurs if FPCON.URDIS=1. Reserved: The value read from this bit is indeterminate. Write zero to this bit. 1 EF 0 -
6 5 4 3
EFSR
2 1
EF
0
-
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4.5.5 EPCON Register Descriptions - USB Function SFRs (E1) Address: S:E1H Reset State(Endpoint 0): 001X 0101H Reset State(Endpoint X): 000X 0000H
Endpoint Control Register (Endpoint-Indexed). This SFR configures the operation of the endpoint specified by EPINDEX. 7 RXSTL Bit Number 7 6 TXSTL Bit Mnemonic RXSTL 5 CTLEP 4 3 RXIE 2 RXEPEN Function Stall Receive Endpoint: Set this bit to stall the receive endpoint. Clear this bit only when the host has intervened through commands sent down endpoint 0. When this bit is set and RXSETUP is clear, the receive endpoint will respond with a STALL handshake to a valid OUT token. When this bit is set and RXSETUP is set, the receive endpoint will NAK. This bit does not affect the reception of SETUP tokens by a control endpoint. Stall Transmit Endpoint: Set this bit to stall the transmit endpoint. Clear this bit only when the host has intervened through commands sent down endpoint 0. When this bit is set and RXSETUP is clear, the receive endpoint will respond will respond with a STALL handshake to a valid IN token. When this bit is set and RXSETUP is set, the receive endpoint will NAK. Control Endpoint: Set this bit to configure the endpoint as a control endpoint. Only control endpoints are capable of receiving SETUP tokens. For W81E381, the endpoint 0 (EPINDEX=0000 0000) is hard-wired to "1", since endpoint 0 is always a control endpoint. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Receive Input Enable: Set this bit to enable data from the USB to be written into the receive FIFO. If cleared, the endpoint will not write the received data into the receive FIFO at the end of reception, but will return a NAK handshake on a valid OUT token if the RXSTL bit is not set. This bit does not affect a valid SETUP token. A valid SETUP token and packet overrides this bit if it is cleared, and place the receive data in the FIFO. 1 TXOE 0 TXEPEN
6
TXSTL
5
CTLEP
4 3
RXIE
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Bit Number 2
Bit Mnemonic RXEPEN
Function Receive Endpoint Enable: Set this bit to enable the receive endpoint. When disabled, the endpoint does not respond to a valid OUT or SETUP token. This bit is hardware read-only and has the highest priority between RXIE and RXSTL. Note: The endpoint 0 is enabled for reception upon reset. Transmit Output Enable: This bit used to enable the data in TXDAT to be transmitted. If cleared, the endpoint returns a NAK handshake to a valid IN token if the TXSTL bit is not set. Transmit Endpoint Enable: This bit is used to enable the transmit endpoint. When disabled, the endpoint does not respond to a valid IN token. This bit is hardware readonly. Note: The endpoint 0 is enabled for transmission upon reset.
1
TXOE
0
TXEPEN
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4.5.6 Register Descriptions - USB Function SFRs (F1) Address: S:F1H Reset State: XXXX X000H
EPINDEX
Endpoint Index Register. This register identifies the endpoint pair. It contains select the transmit and receive FIFO pair and serve as an index to endpoint-specific SFRs. 7 Bit Number 7 6 5 4 3 2:0 6 Bit Mnemonic EPINX2:0 5 4 3 2 EPINX2 Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Endpoint Index Bit 2:0: EPINDEX 7:0 = XXXX X000 Function Endpoint 0 -> Control Read/write = XXXX X001 Function Endpoint 1 -> Bulk In = XXXX X010 Function Endpoint 2 -> Bulk Out = XXXX X011 Function Endpoint 3 -> Interrupt In = XXXX X100 Function Endpoint 4 -> Interrupt Out 1 EPINX1 0 EPINX0
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4.5.7 FADDR Register Descriptions - USB Function SFRs (8F) Address: S:8FH Reset State: 0000 0000H
Function Address Register. This SFR holds the address for the USB function. During bus enumeration, it is written with a unique value assigned by the host. 7 Bit Number 7 6 6 A6 Bit Mnemonic A6 5 A5 4 A4 3 A3 2 A2 Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Programmable Function Address Bit 6: This register is programmed through the commands received via endpoint 0 on configuration, which should be the only time the firmware should change the value of this register. This register is hardware readonly. Programmable Function Address Bit 5: This register is programmed through the commands received via endpoint 0 on configuration, which should be the only time the firmware should change the value of this register. This register is hardware readonly. Programmable Function Address Bit 4: This register is programmed through the commands received via endpoint 0 on configuration, which should be the only time the firmware should change the value of this register. This register is hardware readonly. Programmable Function Address Bit 3: This register is programmed through the commands received via endpoint 0 on configuration, which should be the only time the firmware should change the value of this register. This register is hardware readonly. 1 A1 0 A0
5
A5
4
A4
3
A3
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Bit Number 2
Bit Mnemonic A2
Function Programmable Function Address Bit 2: This register is programmed through the commands received via endpoint 0 on configuration, which should be the only time the firmware should change the value of this register. This register is hardware readonly. Programmable Function Address Bit 1: This register is programmed through the commands received via endpoint 0 on configuration, which should be the only time the firmware should change the value of this register. This register is hardware readonly. Programmable Function Address Bit 0: This register is programmed through the commands received via endpoint 0 on configuration, which should be the only time the firmware should change the value of this register. This register is hardware readonly.
1
A1
0
A0
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4.5.8 RXCNT Register Descriptions - USB Function SFRs (E6) Address: S:E6H Reset State: XXX0 0000H
Receive FIFO Byte-Count Register (Endpoint-Indexed). Store the byte count for the data packet received in the receive FIFO specified by EPINDEX. 7 Bit Number 7 6 5 4 3 2 1 0 6 Bit Mnemonic BC4 BC3 BC2 BC1 BC0 5 4 BC4 3 BC3 2 BC2 Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Receive Byte Count Bit 4: Store received byte count. Maximum is sixteen bytes. Receive Byte Count Bit 3: Store received byte count. Maximum is sixteen bytes. Receive Byte Count Bit 2: Store received byte count. Maximum is sixteen bytes. Receive Byte Count Bit 1: Store received byte count. Maximum is sixteen bytes. Receive Byte Count Bit 0: Store received byte count. Maximum is sixteen bytes. 1 BC1 0 BC0
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4.5.9 Register Descriptions - USB Function SFRs (E4) Address: S:E4H Reset State: 0XX0 0XXXH
RXCON
Receive FIFO Control Register(Endpoint-Indexed). Controls the receive FIFO specified by EPINDEX. 7 RXCLR Bit Number 7 6 Bit Mnemonic RXCLR 5 4 RXFFRC 3 RXISO 2 1 0 -
Function Receive FIFO Clear: Set this bit to flush the entire receive FIFO. All flags in RXFLG revert to their reset states (RXEMP is set; the other flags cleard) and all the read/write pointers and markers are read. The RXISO bit in this register and the RXSEQ bit in the RXSTAT register are not affected by this operation. Hardware clears this bit when the flush operation is completed. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. FIFO Read Complete: Set this bit to release the receive FIFO when data set read is complete. Setting this bit "clears" the RXFIF "bit" in the RXFLG register corresponding to the data set that was just read. Hardware clears this bit after the RXFIF bit is cleared. All data from this data set must have been read. Note: that RXFFRC only works if STOVW and EDOVW are cleared. Receive Isochronous Data: Set this bit to indicate that the receive FIFO is programmed to receive isochronous data and to set up the USB interface to handle an isochronous data transfer. This bit is not reset when the RXCLR bit is set; it must be cleared by firmware. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit.
6 5 4
RXFFRC
3
RXISO
2 1 0
-
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4.5.10 Register Descriptions - USB Function SFRs (E3) RXDAT Address: S:E3H Reset State: XXXX XXXXH
Receive FIFO Data Register (Endpoint-Indexed). Receive FIFO data specified by EPINDEX is stored and read from this register. 7 RD7 Bit Number 7 6 RD6 Bit Mnemonic RD7 5 RD5 4 RD4 3 RD3 2 RD2 1 RD1 0 RD0
Function Receive Data Bit 7: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively. Receive Data Bit 6: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively. Receive Data Bit 5: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively. Receive Data Bit 4: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively. Receive Data Bit 3: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively.
6
RD6
5
RD5
4
RD4
3
RD3
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Bit Number 2
Bit Mnemonic RD2
Function Receive Data Bit 2: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively. Receive Data Bit 1: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively. Receive Data Bit 0: To write data to the receive FIFO, the FIU/HIU writes to this register. To read data from the receive FIFO, the firmware reads from this register. The write pointer and read pointer are incremented automatically after a write and read, respectively.
1
RD1
0
RD0
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4.5.11 Register Descriptions - USB Function SFRs (E5) RXFLG Address: S:E5H Reset State: X0XX 1000
Receive FIFO Flag Register (Endpoint-Indexed). These flags indicate the status of data packet in the receive FIFO specified by EPINDEX. 7 Bit Number 7 6 6 RXFIFO Bit Mnemonic RXFIFO 5 4 3 RXEMP 2 RXFULL 1 RXURF 0 RXOVF
Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Receive FIFO Index Flag (read-only): This read-only flag indicate whether a data packet is updated after each write to RXCNT to reflect the addition of a data packet. Likewise, the RXFIF bit is cleared in sequence after each setting of the RXFFRC bit. The next state table for RXFIFO bit is shown below in single packet mode.
RXFIFO X 0 1 0 1
5 4 3 RXEMP
Operation rev. WP adv. WM adv. WM RXFFRC -->1 RXFFRC -->1
Falg x x x x x
Next RXFIFO unchange 1 1 0 0
Next Flag unchange unchange RXOVF=1 RXURF=1 unchange
Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Receive FIFO Empty Flag (read-only): Hardware sets this flag when the write pointer is as the same location as the read pointer and the write pointer equals the write maker and neither pointer has resoled over. Hardware clears the bit when the empty condition no longer exists. This is not a sticky bit and always tracks the current status of the receive FIFO, regardless of ISO or non-ISO mode.
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Bit Number 2
Bit Mnemonic RXFULL
Function Receive FIFO Full Flag (read-only): Hardware sets this flag when the write pointer has rolled over and equals the read pointer. Hardware clears the bit when the full condition no longer exists. This is not a sticky bit and always tracks the current status of the receive FIFO, regardless of ISO or non-ISO mode. Receive FIFO Under-run Flag: Hardware sets this bit when an additional byte is read from an empty receive FIFO or RXCNT. Hardware does not clear this bit, so you must clear it in firmware. When the receive FIFO under-run, the read point will bit advance-it remains locked in the empty position. Note: that you must check the RXURF flag after reads from the receive FIFO before setting the RXFFRC bit in RXCON. When the bit is set, the FIFO is in an unknown state and all transmissions are "NAK"ed. It is recommended that you reset the FIFO in the error management routine using the RXCLR bit in the RXCON register. Receive FIFO Overrun Flag: Hardware sets this bit when FIU/HIU writes an additional byte to a full receive FIFO or writes a byte count to RXCNT with RXFIFO=1.This is a sticky bit that must be cleared through firmware, although it can be cleared by hardware if a SETUP packet is received after RXOVF error had already occurred. When the receive FIFO overruns, the write pointer will not advance- it remains locked in the full position. Note: that when the bit is set, the FIFO is in an unknown state and all transmissions are "NAK"ed. It is recommended that you reset the FIFO in the error management routine using the RXCLR bit in the RXCON register.
1
RXURF
0
RXOVF
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4.5.12 Register Descriptions - USB Function SFRs (E2) RXSTAT Address: S:E2H Reset State: 0000 0000
Endpoint Receive Status Register (Endpoint-Indexed). Contains the current endpoint status of the receive FIFO specified by EPINDEX. 7 RXSEQ Bit Number 7 6 RXSETUP Bit Mnemonic RXSEQ 5 STOVW 4 EDOVW 3 RXSOVW 2 RXVOID 1 RXERR 0 RXACK
Function Receive Endpoint Sequence Bit(read, condition write): The bit will be toggled on completion of an ACK handshake in response to an OUT token. This bit will be set/cleared by hardware after reception of a SETUP token. This bit can be written by firmware if the RXOVW bit is set when written along with the new RXSEQ value. Note that always verify this bit after writing to ensure that there is no conflict with hardware, which could occurred if a new SETUP token is received. Received Setup Token: This bit is set by hardware when a valid SETUP token has been received. When set, this bit causes received IN or OUT tokens to be "NAK"ed until the bit is cleared to allow proper data management for the transmit and receive FIFOs from the previous transaction. IN or OUT tokens are "NAK"ed even if the endpoint is stalled (RXSTL/TXSTL) to allow a control transaction to clear a stalled endpoint. Clear this bit upon detection of a SETUP token or the firmware ready to handle the data/status stage of control transfer. Start Overwrite Flag (read-only): Set by hardware upon receipt of a DETUP token for any control endpoint to indicate that the receive FIFO is being overwritten with new SETUP data. When set, the FIFO state (RXFIFO and read pointer) resets and is locked for this endpoint until EDOVW is set. This prevents a proper, ongoing firmware read from corrupting the read pointer as the receive FIFO is being cleared and new data is being written into it. This bit is cleared by hardware at the end of handshake phase transmission of the SETUP stage. This bit is used only for control endpoints.
6
RXSETUP
5
STOVW
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Bit Number 4
Bit Mnemonic EDOVW
Function End Overwrite Flag: This flag is set by hardware during the handshake phase of a SETUP stage. It is set after every SETUP packet is received and must be cleared prior to reading the contents of the FIFO. When set, the FIFO state (RXFIF0 and read pointer) remains locked for this endpoint until this bit is cleared. This prevents a prior, ongoing firmware read from corrupting the read pointer after the new data has been written into the receive FIFO. This bit is only used for control endpoints. Note: that make sure the EDOVW bit is cleared prior to reading the contents of the FIFO. Receive Data Sequence Overwrite Bit: Write `1' to this bit to allow the value of the RXSEQ bit to be overwritten. Writing a `0' to this bit has no effect on RXSEQ. This bit always returns `0' when read. The SIE will handle all sequence bit tracking. This bit should be used only when initializing a new configuration or interface. Receive Void Condition (read-only): This bit is set when no valid data is received in response to a SETUP or OUT token due to one of the following conditions: 1. The receive FIFO is still locked; 2. The EPCON register's RXSTL bit is set. This bit does not affect the F/HRXDx, RXERR or RXACK. This bit is set and cleared by hardware. For non-isochronous transactions, this bit is updated by hardware at the end of the transaction in response to valid OUT token. For isochronous transactions, it is not updated until the next SOF. Receive Error Condition (read-only): Set when an error condition has occurred with the reception. Complete or partial data has been written into the receive FIFO. No handshake is returned. The error can be one of the following conditions: 1. Data failed CRC check or bit stuffing error; 2. A receive FIFO goes into overrun of under-run condition while receiving. The bit is updated by hardware at the end of a valid SETUP or OUT token transaction (non-isochronous) or at the next SOF on each valid OUT token transaction (isochronous). The corresponding F/HRXDx bit of F/HIFLG is set when active. This bit updated with RXACK bit at the end of data reception and is mutually exclusive with RXACK. Receive Acknowledged Condition (read-only): This bit is set when data is received completely into a receive FIFO and an ACK handshake is sent. The bit is updated by hardware at the end of a valid SETUP or OUT token transaction (non-isochronous) or at the next SOF on each valid OUT token transaction (isochronous). The corresponding F/HRXDx bit of F/HIFLG is set when active. This bit updated with RXERR bit at the end of data reception and is mutually exclusive with RXERR.
3
RXSOVW
2
RXVOID
1
RXERR
0
RXACK
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4.5.13 Register Descriptions - USB Function SFRs (F6) TXCNT Address: S:F6H Reset State: XXX0 0000H
Transmit FIFO Byte-Count Register (Endpoint-indexed). Stored the byte count for the data packet in the transmit FIFO specified by EPINDEX. 7 Bit Number 7 6 5 4 3 2 1 0 6 Bit Mnemonic BC4 BC3 BC2 BC1 BC0 5 4 BC4 3 BC3 2 BC2 Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Transmit Byte Count Bit 4: Store transmitted byte count. Maximum is sixteen bytes. Transmit Byte Count Bit 3: Store transmitted byte count. Maximum is sixteen bytes. Transmit Byte Count Bit 2: Store transmitted byte count. Maximum is sixteen bytes. Transmit Byte Count Bit 1: Store transmitted byte count. Maximum is sixteen bytes. Transmit Byte Count Bit 0: Store transmitted byte count. Maximum is sixteen bytes. 1 BC1 0 BC0
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4.5.14 Register Descriptions - USB Function SFRs (F4) TXCON Address: S:F4H Reset State: 0XXX 0XXXH
Transmit FIFO Control Register (Endpoint-Indexed). Controls the transmit FIFO specified by EPINDEX. 7 TXCLR Bit Number 7 6 Bit Mnemonic TXCLR 5 4 3 2 Function Transmit FIFO Clear: Set this bit to flush the entire transmit FIFO. All flags in TXFLG revert to their reset states (TXEMP is set; all other flags clear) and all the read/write pointers and makers are reset. The TXISO bit in this register and the TXSEQ bit in the TXSTAL register are not affected by this operation. Hardware clears this bit when the flush operation is completed. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. 1 0 -
6 5 4 3 2 1 0
-
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4.5.15 Register Descriptions - USB Function SFRs (F3) TXDAT Address: S:F3H Reset State (Other Endps): XXXX XXXXH Reset State (Hub Endp 1): XXX0 0000H
Transmit FIFO Data Register (Endpoint-Indexed). Data to be transmitted by the FIFO specified by EPINDEX is first written to this register. 7 TD7 Bit Number 7 6 TD6 Bit Mnemonic TD7 5 TD5 4 TD4 3 TD3 2 TD2 Function Transmit Data Bit 7: To write data to the transmit FIFO, the firmware writes to this register. To read data from the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively. Transmit Data Bit 6: To write data to the transmit FIFO, the firmware writes to this register. To read data format the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively. Transmit Data Bit 5: To write data to the transmit FIFO, the firmware writes to this register. To read data from the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively. Transmit Data Bit 4: To write data to the transmit FIFO, the firmware writes to this register. To read data from the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively. 1 TD1 0 TD0
6
TD6
5
TD5
4
TD4
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Bit Number 3
Bit Mnemonic TD3
Function Transmit Data Bit 3: To write data to the transmit FIFO, the firmware writes to this register. To read data from the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively. Transmit Data Bit 2: To write data to the transmit FIFO, the firmware writes to this register. To read data from the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively. Transmit Data Bit 1: To write data to the transmit FIFO, the firmware writes to this register. To read data from the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively. Transmit Data Bit 0: To write data to the transmit FIFO, the firmware writes to this register. To read data from the transmit FIFO, the Function Interface Unit reads from this register. The write pointer and read pointer and read pointer are incremented automatically after a write and read, respectively.
2
TD2
1
TD1
0
TD0
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4.5.16 Register Descriptions - USB Function SFRs (F5) TXFLG Address: S:F5H Reset State: X0XX 1000H
Transmit FIFO Flag Register (Endpoint-Indexed). These flags indicate the status of data packet in the transmit FIFO specified by EPINDEX. 7 Bit Number 7 6 6 TXFIF0 Bit Mnemonic TXFIF0 5 4 3 TXEMP 2 TXFULL 1 TXURF 0 TXOVF
Function Reserved: The value read from this bit is indeterminate. Write zero to this bit. Transmit FIFO Index Flag (read-only): This read-only flag indicate whether a data packet is present in the transmit FIFO. The bit is updated after each write to TXCNT to reflect the addition of a data packet. Likewise, the TXFIF bit is cleared in sequence after each advance of the read marker to indicate that the set is effectively discarded. You must check the TXFIF0 flab before and after writes to the transmit FIFO and TXCNT for tractability. The next state table for TXFIF0 bit is shown below in single packet mode.
TXFIF0 X 0 1 0 1
5 4 3 TXEMP
Operation rev. RP wr. TXCNT wr. TXCNT adv. RM adv. RM
Flag X X X X X
Next TXFIF0 Unchanged 1 1 0 0
Next Flag Unchanged Unchanged TXOVF=1 TXURF=1 Unchanged
Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Transmit FIFO Empty Flag (read-only): Hardware sets this flag when the write pointer is at the same location as the read pointer and the write pointer equals the write marker and neither pointer has rolled over. Hardware clears the bit when the empty condition no longer exists. This is not a sticky bit and always tracks the current status of the transmit FIFO, regardless of ISO or non-ISO mode.
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Bit Number 2
Bit Mnemonic TXFULL
Function Transmit FIFO Full Flag (read-only): Hardware sets this flag when the write pointer has rolled over and equals the read pointer. Hardware clears the bit when the full condition no longer exists. This is not a sticky bit and always tracks the current status of the transmit FIFO, regardless of ISO or non-ISO mode. Transmit FIFO Under-run Flag: Hardware sets this bit when an additional byte is read from an empty transmit FIFO or TXCNT. If the TXCNT does not agree with the data, hardware sets TXURF. This indicates that the transmitted data was corrupted by a bit-stuffing or CRC error. Hardware does not clear this bit, so you must clear it in firmware. When the transmit FIFO under-runs, the read pointer will not advance-it remains locked in the empty position. When the bit is set, the FIFO is in an unknown state and all transmissions are "NAK"ed. It is recommended that you reset the FIFO in the error management routine using the TXCLR bit in the TXCON register. Transmit FIFO Overrun Flag: Hardware sets this bit when firmware writes an additional byte to a full transmit FIFO or writes a byte count to TXCNT with TXFIF0=1. This is a sticky bit that must be cleared through firmware. When the transmit FIFO overruns, the write pointer will not advance-it remains locked in the full position. Note: that when the bit is set, the FIFO is in an unknown state and all transmissions are "NAK"ed. It is recommended that you reset the FIFO in the error management routine using the TXCLR bit in the TXCON register.
1
TXURF
0
TXOVF
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4.5.17 Register Descriptions - USB Function SFRs (F2) TXSTAT Address: S:F2H Reset State: 0XX0 0000H
Endpoint Transmit Status Register (Endpoint-Indexed). Contains the current endpoint status of the transmit FIFO specified by EPINDEX. 7 TXSEQ Bit Number 7 6 Bit Mnemonic TXSEQ 5 4 TXFLUSH 3 TXSOVW 2 TXVOID 1 TXERR 0 TXACK
Function Transmit Endpoint Sequence Bit (read, conditional write): The bit will be transmitted in the next PID and toggled on a valid ACK handshake. This bit is toggled by hardware on a valid SETUP token. This bit can be written by firmware if the TXCOVW bit is set when written along with the new TXSEQ value. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Reserved: The value read from this bit is indeterminate. Write zero to this bit. Transmit FIFO Packet Flushed (read-only): When set, this bit indicates that hardware flushed a stale ISO data packet from the transmit FIFO due to a TXFIF0=1 at SOF. To guard against a missed IN token in ISO mode, if, with TXFIF0=1, no IN token is received for the current endpoint, hardware automatically flushes the oldest packet and clear TXFIF0=0. Transmit Void Condition (read-only): Write "1" to this bit to allow the value of the TXSEQ bit to be overwritten. Writing "0" to this bit has no effect on TXSEQ. This bit always returns "0" when read. This SIE will handle all sequence bit tracking. This bit should be used only when initializing a new configuration or interface.
6 5 4
TXFLUSH
3
TXSOVW
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Bit Number 2
Bit Mnemonic TXVOID
Function Transmit Void Condition (read-only): A void condition has occurred in response to a valid IN token. Transmit void is closely associated with the NAK/STALL handshake returned by function after a valid IN token, due to the conditions that cause the transmit FIFO to be un-enabled or not ready to transmit. Use this bit to check any NAK/STALL handshake returned by the function. This bit does not affect the F/HTXDx, TXERR or TXACK. This bit is set and cleared by hardware. For non-isochronus transactions, This bit is updated by hardware at the end of the transaction in response to a valid IN token. For isochronous transactions, it is not updated until the next SOF. Transmit Error Condition (read-only): An error condition has occurred with the transmission. Complete or partial data has been transmitted. The error can be one of the following conditions: 1. Data transmitted successfully but no handshake received. 2. Transmit FIFO goes into under-run condition while transmitting. The bit is updated by hardware at the end of the data transmission (nonisochronous) or at the next SOF (ischronous). The corresponding F/HTXDx bit of F/HIFLG is set when active. This bit updated with TXACK bit at the end of data transmission and is mutually exclusive with TXACK. Transmit Acknowledged Condition (read-only): This bit is set when data is transmitted completely and acknowledged successfully. The bit is updated by hardware at the end of data transmission (non-isochronous) or at the next SOF (isochronous). The corresponding F/HRXDx bit of F/HIFLG is set when active. This bit updated with TXERR bit at the end of data transmission and is mutually exclusive with TXERR.
1
TXERR
0
TXACK
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.18 Register Descriptions - USB Device SFRs (B7) DCON Address: Reset State: S:B7H 0000 0000H
Device Control Register. This register contains bits for USB Device connection pull-up enable. 7
TEST_MODE
6
SCGPIOSL
5
SCIOGPE
4
SCIOGPD
3
SCCLKGPE
2
SCCLKGPD
1
PTRWUEN
0
CONPUEN
Bit Number 7 6
Bit Mnemonic SCGPIOSL
Function TEST_MODE enable: Used for test only. In normal operation, this bit should be set to zero. Mode select between normal Smart Card and GPIO pad 0: Smart Card 1: GPIO pad Output enable 0: Enable 1: Disable Smart Card I/O (SCIO) data, when SCIOGPE enable. Output enable 0: Enable 1: Disable Smart Card Clock (SCCLK) data, when SCCLKGPE enable. Path through remote wake-up enable: "1" is enable. If set to zero and remote wake up event occurs in suspend state, device will drive wake up signal to Host after setting the FRWU bit in FPCON register. Otherwise, device will drive wake up signal to Host directly. Device/USP Connection Pull-Up Enable: This bit is used by FW to control whether device is connected to upper host/hub via enable/disable the on-chip pull-up resistor. Set `1' to enable the D+ pull-up resistor; set `0' to disable the D+ pull-up resistor that is D+/D- is kept disconnected state. Default is cleared to `0' after POR, FW should set `1' to enable connection to upper host/hub.
5
SCIOGPE
4 3
SCIOGPD SCCLKGPE
2 1
SCCLKGPD PTRWUEN
0
CONPUEN
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.19 Register Descriptions - USB Device SFRs (BF) SCON Address: Reset State: S:BFH 1011 0000H
SIE Control Register1: This register contains bits for SIE using RXD enable, SIE LS enable, SIE CRC16-based EOP check patch, SIE time-out detection patch, SIE end-of-sync detection modes, SIE EOP detection modes control. 7
SIERXDE
6
SIELSE
5
SECKPAT
4
STODPAT
3
SEOSMOD1
2
SEOSMOD0
1
SEOPMOD1
0
SEOPMOD0
Bit Number
7
Bit Mnemonic
SIERXDE
Function
SIE Using RXD Enable: (Reserved for test only) The bit is used to select either the differential receiver output RXD (UBPRXD) or the single-ended receiver output RXDP/RXDM (VPIN/VMIN) as the received serial data for SIE input. Set `1', SIE uses RXD (UBPRXD); set `0', SIE used RXDP/RXDM (VPIN/VMIN). Default is set to `1' (using RXD= UBPRXD) after power-on-reset. SIE Low-Speed Enable: (Reserved for test only) The bit is used to select SIE operated either in Low-Speed Mode or in FullSpeed Mode. Set `0' SIE operate in Full-Speed Mode; set `1', SIE operates in Low-Speed Mode. Normally, Hub/SIE is default set to full-speed mode (i.e. cleared to `0') after power-on-reset. SIE CRC16-Based EOP Check Patch Enable: (Reserved for test only) This bit is used by FW to enable the patch for SIE detecting CRC16-based EOP=K/J001 with K/J=(80+80)ns and 00=3*SE0=(160+80)ns. `1' is patch enabled; `0' is patch disabled. Default is set to `1' after POR. SIE Time-Out Detection Patch Enable: (Reserved for test only) This bit is used by FW to enable the patch for SIE detecting time_out_16 bug during waiting for CRC5-based EOP. `1' is patch enabled; `0' is patch disabled. Default is set to `1' after POR. SIE EOS Detection Modes: (Reserved for test only) These bits are used to select one of the following SIE EOS (End-Of-Sync) detection modes: 00 - SYNC Pattern = "- -JKJKK" (Default) 01 - SYNC Pattern = "- -J -JKK" 10 - SYNC Pattern = "- - -KJKK" 11 - SYNC Pattern = "- - - -JKK" Repeater EOP Detection Modes: (Reserved for test only) These bits are used to select one of the following repeater EOP detection modes: 00 - Normal Mode (Default) 01 - Relax Mode 1 10 - Relax Mode 2 11 - Relax Mode 3
6
SIELSE
5
SECKPAT
4
STODPAT
3:2
SEOSMOD1:0
1:0
SEOPMOD1:0
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.20 Register Descriptions - SC Interrupt SFRs (AA) SCIER Address: S:AAH Reset State: 0000 0000H
Interrupt Control Register of Smart Card Reader (SCIEL). Contains all control for interrupt enable from smart card interface. 7 - 6 ESCPTI 5 WCE 4 - 3 PBE 2 RDRE 1 EXIE 0 -
Bit Number 7 6 5 4 3 2 1 0
Bit Mnemonic ESCPTI WCE RDRE PBE EXIE Reserved
Function
1: Enable SC present toggle interrupt request 0: Disable SC present toggle interrupt request 1: Enable wrong card interrupt 0: Disable wrong card interrupt Reserved To enable RX data ready interrupt To enable the parity check function To enable external interrupt Reserved
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.21 Register Descriptions - SC Interrupt SFRs (AB) SCISR Address: S:ABH Reset State: 0000 0000H
Interrupt Status Register of Smart Card Reader (SCISL). Contains all interrupt status of smart card interface. 7 Bit Number 7 6 5 4 3 2 1 0 6 SCPTI Bit Mnemonic SCPTI WCI TDI RDRI PBRI EXI EXI_16 Reserved The Toggle Interrupt of SCPRSNT An interrupt of Wrong Card or abnormal card Ending of TX data interrupt (rising at guard time ending) Received Data buffer Ready Interrupt (rising at parity check bit ending) Parity Bit eRror Interrupt EXternal Interrupt input from P1.7 Remote wakeup input from P1.6 5 WCI 4 TDI 3 PBER 2 RDR 1 EXI 0 EXI_16
Function
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.22 Register Descriptions - SC Control SFRs (A3) SCSR Address: S:A3H Reset State: 0000 0000H
Status Register of Smart Card Reader (SCSR). 7 Bit Number 7 6 5 4 3 2 1 0 6 Bit Mnemonic SCPRSNT CA Reserved Reserved Reserved Reserved Smart Card is PReSeNT Reserved Reserved Read/Write Cycle Active indicator 5 4 3 SCPRSNT Function 2 1 0 CA
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.24 Register Descriptions - SC Control SFRs (AC) SCCR Address: S:ACH Reset State: 0001 0110H
Control Register of Smart Card Reader (SCCR). 7 Bit Number 7 6 5 4 6 Bit Mnemonic CLKSTPL Reserved Reserved Reserved SC clock polarity control bit during stopping clock (corporate with CLKSTP of SCECR) 1: Indicate the SCCLK pin stays in High as clock stopped 0: Indicate the SCCLK pin stays in Low as clock stopped Bit 1 of selecting the SC clock frequency Bit 0 of selecting the SC clock frequency
{S_CK1, S_CK0} 00 01 10 11 1.5MHz 3MHz 4MHz 6MHz
5 -
4 CLKSTPL
3 S_CK1
2 S_CK0
1 EPE
0 EXINTH
Function
3 2
S_CK1 S_CK0
1 0
EPE EXINTH
1: To do even parity check 0: To do odd parity check The polarity of external interrupt 1: Indicate external interrupt input is High active 0: Indicate external interrupt input is Low active
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.25 Register Descriptions - SC Control SFRs (AD) SCECR Address: S:ADH Reset State: 0000 0000H
Extended Control Register of Smart Card Reader (SCECR). 7 CRDRST Bit Number 7 6 PWRENP Bit Mnemonic CRDRST 5 VCC_EN 4 - 3 - 2 CLKSTP Function To issue a reset signal to SC 1: High -> Low 0: Low -> High To determine the polarity of the VCC_EN signal If WCE=0 => 1: Positive, 0: Negative If WCE=1 => 0: Positive, 1: Negative 1: Enable SC power supply 0: Disable SC power supply Reserved Reserved 1: To stop the SC clock 0: To start the SC clock SCIO direction control signal. 1: Transmit data to card 0: Receive data from card Resynchronize SC interface (reload default value to SC related registers, include itself) 1 SCIO 0 SCRRST
6
PWRENP
5 4 3 2 1
VCC_EN CLKSTP SCIO
0
SCRRST
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.26 Register Descriptions - SC Control SFRs (AE, A4)
SCGTR Address: S:AEH Reset State: 0000 0000H
Guard Time Register of Smart Card Reader (SCGTR). 7 BIT 7 Bit Number 7 6 5 4 3 2 1 0 6 BIT 6 Bit Mnemonic BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 Function 1 BIT 1 0 BIT 0
SCBDR
Address: S:A4H Reset State: 0000 0001H
Baud Rate Divider Register of Smart Card Reader (SCBDR). 7 BIT 7 Bit Number 7 6 5 4 3 2 1 0 6 BIT 6 Bit Mnemonic BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 Function 1 BIT 1 0 BIT 0
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.27 Register Descriptions - SC Control SFRs (A5) SCCBR Address: S:A5H Reset State: 0000 0001H
Clock Base Register of Smart Card Reader (SCCBR). 7 BIT 7 Bit Number 7 6 5 4 3 2 1 0 6 BIT 6 Bit Mnemonic BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 5 BIT 5 4 BIT 4 3 BIT 3 2 BIT 2 1 BIT 1 0 BIT 0
Function
Ps: The value of (SCCBR X SCBDR) is the same as the definition of Q (Q=F/D) in ISO-7816 specification.
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.28 Register Descriptions - SC Data SFRs (A6, A7)
SCRDR Address: S:A6H Reset State: 0000 0000H
Received Data Register of Smart Card Reader (SCRDR). 7 RD 7 Bit Number 7 6 5 4 3 2 1 0 SCTDR 6 RD 6 Bit Mnemonic RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0 Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 Address: S:A7H Reset State: 0000 0000H 5 RD 5 4 RD 4 3 RD 3 2 RD 2 Function 1 RD 1 0 RD 0
Transmitted Data Register of Smart Card Reader (SCTDR). 7 TD 7 Bit Number 7 6 5 4 3 2 1 0 6 TD 6 Bit Mnemonic TD 7 TD 6 TD 5 TD 4 TD 3 TD 2 TD 1 TD 0 Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 5 TD 5 4 TD 4 3 TD 3 2 TD 2 Function 1 TD 1 0 TD 0
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.29 Register Descriptions - ISP Registers (C4, C5)
SFRAL Address: S:C4H Reset State: 0000 0000H
Special Function Register Address Low Register (SFRAL). Low-byte of programming address for on-chip flash. 7 LA7 Bit Number 7 6 5 4 3 2 1 0 SFRAH 6 LA6 Bit Mnemonic LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: S:C5H Reset State: 0000 0000H 5 LA5 4 LA4 3 LA3 Function 2 LA2 1 LA1 0 LA0
Special Function Register Address High Register (SFRAH). High-byte of programming address for on-chip flash. 7 HA7 Bit Number 7 6 5 4 3 2 1 0 6 HA6 Bit Mnemonic HA7 HA6 HA5 HA4 HA3 HA2 HA1 HA0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 HA5 4 HA4 3 HA3 2 HA2 Function 1 HA1 0 HA0
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.30 Register Descriptions - ISP Registers (C6, C7)
SFRFD Address: S:C6H Reset State: 0000 0000H
Special Function Register Flash Data Register (SFRFD). The programming data register for on-chip flash. 7 FD7 Bit Number 7 6 5 4 3 2 1 0 SFRCN 6 FD6 Bit Mnemonic FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: S:C7H Reset State: 0011 0000H 5 FD5 4 FD4 3 FD3 Function 2 FD2 1 FD1 0 FD0
Special Function Register Flash Control Register (SFRCN). The programming control register for on-chip flash. 7 Bit Number 7 6 5 4 3 2 1 0 6 Bit Mnemonic OEN CEN CTRL3 CTRL2 CTRL1 CTRL0 Reserved Reserved Ouput enable control of flash memory 0/1: Enable/Disable Chip enable control of flash memory 0/1: Enable/Disable Bit 3 of flash memory control mode Bit 2 of flash memory control mode Bit 1 of flash memory control mode Bit 0 of flash memory control mode 5 OEN 4 CEN 3 CTRL3 2 CTRL2 1 CTRL1 0 CTRL0
Function
Note: Refer the ISP related SFR usage in Section4.6 Publication Release Date: January 2002 Revision 0.52
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W81E381D/W81E381AD
4.5.31 Register Descriptions - uC Control Registers (CF)
CHPCON
Address: S:CFH Reset State: 0000 0000H
On-chip Programming Control Register (CHPCON). Select the delay period of oscillation when waking up from power-down mode. 7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
FPROGEN
Bit Number 7 6 5 4 3 2 1 0
Bit Mnemonic -
Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved MTP-ROM Programming Enable 1: Enable. The micro controller switches to the programming flash mode after entering the idle mode and waken up from interrupt. The microcontroller will execute the loader program while in on-chip programming mode. 0: Disable. The on-chip flash memory is read-only. In-system program ability is disabled.
FPROGEN
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.5.32 Register Descriptions - uC Control Registers (D4, D5)
PMPR2 Address: S:D4H Reset State: 0000 0000H
Program Memory Protection Register2 (PMPR2). To configure the blocks of flash memory under protection. 7 Bit Number 7 6 5 4 3 2 1 0 PMPR1 6 Bit Mnemonic HBP1 HBP0 Reserved Reserved Reserved Reserved Reserved Reserved To protect 0x4800-0x4fff block To protect 0x4000-0x47ff block Address: S:D5H Reset State: 0000 0000H 5 4 3 Function 2 1 HBP1 0 HBP0
Program Memory Protection Register1 (PMPR1). To configure the blocks of flash memory under protection. 7 LBP7 Bit Number 7 6 5 4 3 2 1 0 6 LBP6 Bit Mnemonic LBP7 LBP6 LBP5 LBP4 LBP3 LBP2 LBP1 LBP0 To protect 0x3800-0x3fff block To protect 0x3000-0x37ff block To protect 0x2800-0x2fff block To protect 0x2000-0x27ff block To protect 0x1800-0x1fff block To protect 0x1000-0x17ff block To protect 0x0800-0x0fff block To protect 0x0000-0x07ff block 5 LBP5 4 LBP4 3 LBP3 2 LBP2 1 LBP1 0 LBP0
Function
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
4.6 MTP-ROM PROGRAMMING
The context of flash in W81E381 is empty by default. At the first use, you must program the flash by external writer device. For programming the flash by external device, the W81E381 must enter the flash-programming mode by power on reset. The setting conditions and the timing are following. Especially to illustrate, if you only want to erase one block (512 bytes), not to erase all (20k bytes), you have to use the in-system-programming function to do the operation.
Mode Standby Read 16KB APROM Read 4KB LDROM Program 16KB APROM Program 4KB LDROM Check board Erase All Erase 16KB APROM Erase 512Byte Read ROM_MAP Program ROM_MAP Erase ROM_MAP Read Company ID Read Device ID 16KB program verify 4KB program verify 16KB erase verify 4KB erase verify 16KB VT mode 4kB VT mode 16KB Read-Disturb 4KB Read-Disturb SFRAH<6> (A<14>) X 0 1 0 1 X X 0 0 0 0 0 X X 0 1 0 1 0 1 0 1 SFRCN<5> (FOEN) 1 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 SFRCN<4> (FCEN) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFRCN<3:0> (FCTRL<3:0>) X 0000 0000 0001 0001 1000 0110 0010 1111 0011 0100 0101 1011 1100 1010 1010 1001 1001 1101 1101 1110 1110 SFRAH, SFRAL (A<13:0>) X Address in Address in Address in Address in Address in X X Address in FFFF H FFFF H FFFF H X X Address in Address in Address in Address in Address in Address in Address in Address in SFRFD (D<7:0>) X Data out Data out Data in Data in Data in X X X Data out Data in X DA H 62H / 61H Data out Data out Data out Data out Current Current Data out Data out
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
5. SECURITY
During the on-chip MTP-ROM programming mode, the MTP-ROM can be programmed and verified repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The protection of MTP-ROM and those operations on it are described below. W81E381 has some Special Setting Registers, including the Security Register and Company/Device ID Registers, which can't be accessed in programming mode. Those bits of the Security Registers can't be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The contents of the Company ID and Device ID registers have been set in factory. The Security Register is located at the FFFFH.
1 0
1 1
0 1
1 0
0 0
0
1
0
Com pany ID (#DA H ) Device ID (#62H or #61H ) Security Bits
On -C hip Program M em ory
0000 H
0 0/1 0/1
B7 B6 B5 B4 B3 B2 B1 B0
Bit 7 : 1 - > 24 M Hz
0 - > 12 M Hz ( Crystal Select )
Bit 1 : 0 - > M OVC lock Default 1 for each bit.
O ption B yte
4 FFFH FFFFH
Special Setting R egisters
MOVC Lock: This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the program to be downloaded using this instruction if the program needs to jump outside to get data. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code in the external memory, but it will not be able to access code in the internal memory. A MOVC instruction in internal program memory space will always be able to access code in both internal and external memory. If this bit is logic 1 (default), there is no restriction on the MOVC instruction. Crystal Select If this bit is set to logic 1, uC uses internal 24Mhz input. If this bit is set to logic 0, W81E381 could use external crystal source.
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
6. ELECTRICAL CHARACTERISTICS
Operating conditions: VCC = 4.0V to 5.25V, Ta=0 to 70 C PARAMETER VCC Supply Current VCC Suspend Current Logic Output High Logic Output Low Logic Input High Logic Input Low Logic Input Leakage Current USB CHARACTERISTICS Leakage Current: Hi-Z State Output Leakage Input Levels: Differential Input Sensitivity Single Ended Signal "0" Differential Common Mode Range Output Levels: Driver Output Low Driver Output High Output Signal Crossover Voltage Capacitance: Transceiver Capacitance Full Speed Timings: Output Rise/Fall Times Source Differential Driver Jitter to Next Transition / to Paired Transition Differential to EOP transition Skew Hub Differential Data Delay(without cable) Hub Differential Driver Jitter to Next Transition / to Paired Transition (including cable) Data bit width distortion after SOP Hub SE0 Delay Relative to t HDD Hub EOP Output Width Skew t R /t F t DJ1 /tDJ2 t DEOP t HDD2 t HDJ1 / t HDJ2 t SOP t EOPD t HESK Note 1, 4 (CL= 50 pF) Note 2, 3 Note 3 Note 2,3,5 Note 2,3,5 Note 3,5 Note 3,5 Note 3,5 -3 / -1 -5 0 -15 4 -3.5 /-4 -2 20 3.5 /4 5 44 3 /1 5 15 15 ns ns ns ns ns ns ns ns ns CIN Pin to GND 20 pF VOLU VOHU VCRS RL of 1.5 k to 3.6 V RL of 15 k to GND 2.8 1.3 0.3 3.6 2.0 V V V VDI VSE0 VCM Includes VDI range |(D+)-(D-)| 0.2 0.8 0.8 2.0 2.5 V V ILO V< V IN <3.3 V -10 +10 uA Symbol Icc Ipd VOH VOL VIH VIL Ta=70 C Note 8
o o o
Conditions
Min
Max TBD TBD
Unit mA uA V V V V uA
IOH=-3mA IOL=3mA
2.4 2.0
VCC 0.4 0.8 10
Note 1: Measured from 10% to 90% of the data signal. Note 2: Timing difference between the differential signals. Note 3: Measured at crossover point of differential data signals. Note 4: The rising and falling edges should be smoothly transition (monotonic). Note 5: Full Speed timing has a 1.5 k pull-up to 2.8 V on the D+ (DP) data line. Note 7: The maximum load specification is the maximum effective capacitive load allowed that meets the target hub VBUS droop of 330 mV. Note 8: Other USB Electrical Characteristics refer to USB spec Rev1.1 Sec7.3.2 and Sec7.3.3.
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
7. MECHANICAL INFORMATION
7.1 W81E381D 48 LQFP (7x7x1.4mm footprint 2.0mm) PACKAGE
H
36
25 24
37
H
48
13
1
12
Controlling dimension : Millimeters
Symbol
Dimension in inch
Dimension in mm
Min Nom Max
0.002 0.004 0.053 0.055 0.006 0.008 0.004 0.006 0.272 0.276 0.272 0.276 0.014 0.350 0.350 0.018 0.020 0.354 0.354 0.024 0.039 0.004 0 7 0.006 0.057 0.010 0.008 0.280 0.280 0.026 0.358 0.358 0.030
Min Nom Max
0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.10 0 7 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75
A A1 A2 b c D E e HD HE L L1 Y 0
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
7.2 W81E381AD 100 LQFP (14x14x1.4 mm footprint 2.0mm) PACKAGE
HD D 7 7 51 50 A A2
A1
HE E
100 1 e b 25
26 L c L1
Y
Controlling Dimension : Millimeters
Symbol A A1 A 2 b c D E e HD HE L L1 y 0 0.002 0.053 0.007 0.004 0.547 0.547 0.622 0.622 0.018 0.055 0.009 0.006 0.551 0.551 0.020 0.630 0.630 0.024 0.039 0.004 7 0 0.638 0.638 0.030 15.80 15.80 0.45 0.057 0.011 0.008 0.556 0.556 Dimension in inch Min Nom Max 0.063 Dimension in mm Min Nom Max 1.60 0.05 1.35 0.17 0.10 13.90 13.90 1.40 0.22 0.15 14.00 14.00 0.50 16.00 16.00 0.60 1.00 1.45 0.27 0.20 14.10 14.10 16.20 16.20 0.75 0.10 7
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
8. TYPICAL APPLICATION
8.1 W81E381D reference schematic
E381D Smart Card Ref Sch
USB Indicator(F/W optional) DVDD C2 + 10u DVSS DVDD AVDD AVSS V3.3 1 2 5 19 20 38 39 3 4 6 7 29 27 21 41 48 36 37 34 35 42 43 44 45 U1 AVDD AVSS V33 DVSS DVDD DVSS DVDD USBDP USBDM SDA SCL RST PLLEN RVED1 RVED2 RVED3 XTAL-I XTAL-O P3.0 P3.1 P3.4 P3.5 P3.6 P3.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.2 UC-XO UC-XI SCPWR SCIO SCCLK SCRST SCPRSNT 46 47 8 9 15 16 17 18 10 11 12 13 14 22 25 26 28 23 24 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.2 UC-XO UC-XI SCIO SCCLK SCRST P1.2 1 D1 LED 2 R1 330 DVDD C3 R2 7.5K Remote Wakeup(optional) BUTTON P1.6 S1 DVDD L1 FB USBDM USBDP 0.1u JP1 USB-CON-B 1 2 3 4 L2 *P1.7 could be programed as external INT FB 5 6 + C1 10u
Place near chip USBDP USBDM R3 R4 C4 15p C5 15p 30 30
SDA SCL RST PLLEN
XI XO P3.0 P3.1 P3.4 P3.5 P3.6 P3.7
SCPWR 33 30 R5 100 31 R6 100 32 R7 100 SCPRSNT 40
W381-48LQFP
DVDD
2nd Xtal source - optional
XO R8 0 Y1 C10 30p 6MHz XI C11 30p C12 30p R9 0 Y2 6MHz UC-XI C13 30p DVSS L4 FB UC-XO DVDD L3 FB AVDD C7 0.1u AVSS C8 0.1u C9 0.1u DVDD RST
C6 + 10u
R10 4.7K
DVDD I/O port P0.0 P0.2 P0.4 P0.6 JP2 1 3 5 7 2 4 6 8 P0.1 P0.3 P0.5 P0.7 R12 2 D2 LED 470 C14 0.1u C15 10u 1 + R14 Ru Q1 SCPWR SC-SOCKET U2 SC-5V SCRST SCCLK SCC4 SCPRSNT 1 2 3 4 9 SCPWR SCRST SCCLK SCC4 9 SC-SOCKET R16 Ru SW SPST R17 10K SCGND SCC6 SCIO SCC8 10 5 6 7 8 10 SCGND SCC6 SCIO SCC8 DVDD C16 30p R15 Ru R11 20K R13 Ru SC-5V SC-5V
MOSFET P
HEADER 4X2
P2.2
1
JP3 TP JP4 1 3 5 7 2 4 6 8
P1.6 P1.0 P1.2 P1.4 P1.6
P1.1 P1.3 P1.5 P1.7
HEADER 4X2 P3.0 P3.4 P3.6 JP5 1 3 5 2 4 6 P3.1 P3.5 P3.7
*Ru is reserved for future using
HEADER 3X2 Size Date:
WINBOND ELECTRONICS CORP. Document Number E381D Smart Card Ref Sch - 48 LQFP Friday, August 31, 2001 Sheet 1 of 1 Rev 0.2
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
8.2 W81E381AD reference schematic
E381 General ref sch
AVDD C2 + 10u DVSS DVDD AVSS V3.3 1 2 3 6 37 38 81 82 4 5 8 9 79 80 11 12 53 95 61 39 86 96 97 45 46 100 100 100 63 64 65 66 83 U1 AVDD AVSS V33GND V33 DVSS DVDD DVSS DVDD USBDP USBDM SDA SCL XTAL-I XTAL-O SOFTCNEN TESTENB PLLEN XCVREN RST PSEN ALE /EA UC51EN UC_XO UC_XI SCIO SCCLK SCRST SCPWR SCPRSNT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 93 94 14 15 29 31 32 33 16 18 19 26 27 43 51 52 41 42 55 56 57 59 60 84 68 69 35 36 88 89 90 91 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 DVDD USB/SMC Indicator(F/W optional) DVDD P1.2 1 D1 LED D2 LED 2 R2 330 2 R5 330 L2 FB DVDD L1 R1 7.5K C3 0.1u JP1 USB-CON-B 1 2 3 4 5 6 C1 + 10u
Place near chip USBDP USBDM R3 R4 C4 15p C5 15p 30 30
SDA SCL XI XO SOFTCNEN TESTENB PLLEN XCVREN RST PSEN ALE /EA UC51EN UC_XO UC_XI
P1.3
1
FB USBDM USBDP
Remote Wakeup(optional) BUTTON P1.6 S1
SCIO SCCLK SCRST
R6 R7 R8
Reserved for future use *P1.7 could be programed as external INT DVDD P1.0 SCC4 P3.0 JP2 1 3 5 2 4 6 P1.1 SCC8 P3.1
SCPWR SCPRSNT
W381-100LQFP
C6 + 10u RST
HEADER 3X2
R9 4.7K DVDD I/O port P0.0 P0.2 P0.4 P0.6 JP3 1 3 5 7 2 4 6 8 P0.1 P0.3 P0.5 P0.7 DVDD P2.1 P2.3 P2.5 P2.7 Q1 2nd Xtal source UC_XO R10 0 Y1 P1.1 P1.3 P1.5 P1.7 C9 Xp XMHz UC_XI C10 Xp C11 30p R11 0 Y2 6MHz R13 2 XI C12 30p D3 LED 470 C7 0.1u C8 10u 1 + XO MOSFET P SC-5V SCRST SCCLK SCC4 DVSS L4 FB L3 FB AVDD
AVSS
HEADER 4X2 P2.0 P2.2 P2.4 P2.6 JP4 1 3 5 7 2 4 6 8
SCPWR SC-SOCKET U2 1 2 3 4 9 SCPWR SCRST SCCLK SCC4 9 SC-SOCKET R17 Ru SW SPST R18 10K SCGND SCC6 SCIO SCC8 10 5 6 7 8 10 SCGND SCC6 SCIO
SC-5V SC-5V R12 20K R14 Ru SCC8 DVDD C13 30p R16 Ru
HEADER 4X2 P1.6 P1.0 P1.2 P1.4 P1.6 JP5 1 3 5 7 2 4 6 8
R15 Ru
SCPRSNT
HEADER 4X2 P3.0 P3.2 P3.4 P3.6 JP6 1 3 5 7 2 4 6 8 P3.1 P3.3 P3.5 P3.7
HEADER 4X2 <- Depend on F/W choose DVDD *Ru is reserved for future using Default-High
C14 External ROM & RAM Optional 0.1u
C15 0.1u
C16 0.1u
WINBOND ELECTRONICS CORP. Size Document Number CustomE381 General ref sch - 100 LQFP Date: Friday, August 31, 2001 Sheet 1 of 1 Rev 0.1
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Publication Release Date: January 2002 Revision 0.52
W81E381D/W81E381AD
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 63 -
Publication Release Date: January 2002 Revision 0.52

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